The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a SOI (Silicon On Insulator) type semiconductor device and a method of manufacturing the same.
As the reduction in power consumption of semiconductor integrated circuits and the enhancement in mounting density thereof are furthered, the miniaturization of the individual elements constituting the integrated circuits and the lowering in operating voltages thereof are strongly desired. In the case of a conventional bulk planar type elements, as a result of the miniaturization of the elements and the reduction in channel length thereof, a short-channel effect is actualized; and, in order to prevent it, technical measures such as the enhancement of the impurity density in the substrate, the thinning of the gate insulator, etc. have been taken in accordance with several element size-reduction rules. However, as a matter of fact, as the elements are further and further miniaturized, the existence of some physical limits is encountered; and thus, in order to achieve a further miniaturization, some novel element structures have come to be proposed. As one such novel element structure, there can be pointed out a SOI element which has an insulator under an active region thereof.
Next, typical examples of the structure of an SOI element and the method of the manufacturing the same will be described below. First, FIG. 1 shows a sectional view taken along the direction of the channel length of the SOI element. On a monocrystalline silicon (Si) semiconductor substrate 1, a monocrystalline silicon (Si) active layer 3 is formed through, e.g. a silicon oxide layer (SiO2) 2, and further, a gate electrode 9 is formed through, e.g. a silicon oxide layer (SiO2) 8 which is to be used as a gate insulator. Further, a source region 4-1 and a drain region 4-2 are formed by introducing, by the use of ion implantation method, an impurity of the conductivity type opposite to that of a silicon active layer 4-3 which is to be used as a channel region.
However, the SOI element which has thus been formed is advantageous, in view of improving the element characteristics thereof, in that the film thickness of the active layer can be reduced, but on the other hand, due to the fact that the source and drain diffusion layers or the depletion layer extending from the source and drain diffusion layers reach even the insulator lying under the active layer, it is it is structurally difficult to control the potential in the body region so easily as in the case of a conventional bulk planar type element. As a result, there takes place the phenomenon that the potential in the body region floats during the operation of the element, thus posing problems such as the problem that, during the operation of the element, the threshold voltage of the element changes.
As countermeasures to these problems, attempts have been made to control the potential in the channel region of the thin-film SOI element.
For instance, in Japanese Patent Publication (KOKAI) No. 61-34978, it is proposed to form an electrode, between the isolation region and the buried insulator thereunder, for providing a potential to the channel region from outside. According to this method, however, the isolation insulator is formed in such a manner that the isolation region is previously oxidized into a thin film by selectively controlling the amount thereof, and further, the thicknesses of the contact portion to the channel region and the isolation region are controlled simultaneously and repeatedly again to form the isolation dielectric. Thus, the method has the problem or defect that it is very difficult to control the amount of the SOI layer at the respective manufacturing steps for the reduction in thickness of the SOI layer intended in view of improving the performances, and at the same time, the increase in the necessary area occupied by the element is increased.
As described above, mainly in the case of a conventional thin-film SOI element, there are problems or defects such as the defect that the manufacturing steps thereof become complicated as compared with the formation of a conventional bulk planar type element, and further, the area occupied by the element is substantially increased.
It is the object of the present invention to provide, mainly, a SOI type semiconductor device and a method of manufacturing the semiconductor device, according to which the miniaturization of the semiconductor device, the enhancement in operating speed thereof, and the reduction in power consumption thereof can be realized.
To achieve the above subject, according to the present invention, the following means are employed.
The main point of the present invention lies in that, in the step of forming the isolation region, the isolation width thereof and the formation condition thereof are varied, whereby, in a desired area, a region in which an isolation layer formed from the surface of a channel layer does not extend as far as an insulator positioned under an active layer which lies under the isolation layer is formed in a self-aligning manner, and, through the region, a region for controlling the potential in a body region is formed.
The semiconductor device according to the present invention comprises a semiconductor substrate having a first insulator, and a semiconductor channel region formed on the first insulator, wherein the semiconductor channel region comprising at least two first regions both having the first conductivity type, a second region of the conductivity type opposite to the first conductivity type, the second region being provided between the two first regions, a second insulator formed on the second region, a gate electrode formed on the second insulator, a third region having the same conductivity type as that of the second region, the third region being electrically conductive to the second region, a third insulator formed on the third region, the third insulator having a width narrower than the widths of an isolation region for isolating the semiconductor formation region, and a fourth region of the same conductivity type as that of the third region, the fourth region being electrically conductive to the third region. In connection with this, it is preferable that the gate electrode is formed on the second region and the fourth region. Further, it is effective that the gate electrode is electrically conductive to the fourth region, and the gate electrode is formed on the fourth region through a fourth insulator.
The above-mentioned method of manufacturing a semiconductor device according to the present invention comprises the step of forming the third insulator simultaneously with the formation of the isolation region by making the interval between the second region and the fourth region narrower than the width of the isolation region at the time of forming the isolation region so as to extend as far as the first insulator in order to isolate the semiconductor channel region.
Further, the method of manufacturing a semiconductor device, which comprises a semiconductor substrate having a first insulator and a semiconductor channel region formed on the first insulator, the semiconductor channel region including at least two first regions of a first conductivity type, a second region provided between the first regions and having the conductivity type opposite to the first conductivity type, a second insulator formed on the second region, a gate electrode formed on the second insulator, a third region having the same conductivity type as that of the second region and being electrically conductive to the second region, a third insulator formed on the third region, and a fourth region having the same conductivity type as that of the third region and being electrically conductive to the third region, according to the present invention comprises the step of forming the third insulator simultaneously with the formation of the isolation region by narrowing the interval between the second region and the fourth region than the width of the isolation region at the time of forming the isolation region so as to extend as far as the first insulator in order to isolate the semiconductor channel region. In connection with this, it is preferable that the gate electrode is formed on the second region and the fourth region. Further, it is effective that the gate electrode is electrically conductive to the fourth region, and the gate electrode is formed on the fourth region through a fourth insulator.
By using the above-mentioned method, the electrode for controlling the potential in the body region can be formed without complicating the manufacturing steps as compared with the conventional bulk planar type element and by suppressing the increase of the area required. As a result, the problem pertaining to the floating effect of the body potential can be eliminated, and further, the body potentials of the individual elements can be arbitrarily controlled, so that a circuit operation etc. which could not be realized through the conventional bulk planar type elements can be achieved.
As mentioned above, according to the present invention, it is made possible, by controlling the width and film thickness of the isolation region, to form a thin-film SOI element in which the body potential can be controlled without increasing the number of manufacturing steps, complicating the structure of the element or increasing the area occupied by the element.
Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention. The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.